Electron Holography of CMOS Devices with Epitaxial Layers
نویسنده
چکیده
Epitaxial SiGe and SiC(P) layers are used in the Source and Drain regions of the CMOS device to increase hole or electron mobility by imposing compressive (for p-FET device) or tensile (for n-FET device) stress in the channel region of the device [1,2]. Mapping of electrostatic potential in such devices with electron holography faces two new issues. First, the mean inner potential (MIP) of the epi layer Vepi(r) should be known, because it needs to be subtracted from the total potential available from the reconstructed phase image (r):
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